The subject application relates to digital image memory allocation and control systems and methods. While the systems and methods described herein relate to digital image memory allocation and control and the like, it will be appreciated that the described techniques may find application in other memory allocation and control systems, other xerographic applications, and/or other memory allocation and control methods.
Classical multifunction xerographic products use block based electronic precollation (EPC) memory allocations for scan, mark, and middle function operations (rotation, N-up, etc). Since some form of data compression is used for most operations that store (write) image data to memory (such as scanning originals for copying), the amount of memory blocks needed for these operations is not known ahead of time. Therefore, these systems typically use controller interrupts to signal software to dynamically allocate each memory block in real time from a list of free blocks. The real-time overhead for processing these controller interrupts is considerable and especially undesirable in high performance color systems. Since many of these systems are developed with single board/single processor architectures in order to save cost, it becomes desirable to minimize processing (and memory usage) requirements while maximizing system performance and MFD speeds.
Methods have been proposed to dynamically predict storage requirements and also to eliminate most of the interrupts needed to allocate physical memory blocks for compressed images. Although using these methods can certainly greatly increase system performance, there may be some amount of extra memory assigned to each stored image that may not always be needed, since there may be some images that compress to a size substantially less than the prediction. Since in these methods there may be only one interrupt generated by compression completion it is not known how many predicted and assigned blocks actually were “consumed” by the image. A solution is needed to determine how many memory blocks actually comprise each compressed image and trim the memory block list as well as control which blocks generate interrupts for use in implementing memory thresholds for image sizes larger than predicted. This makes memory usage more efficient and is especially desirable in low cost multifunction systems where EPC memory buffers may be allocated in the single CPU memory system. In higher performance systems with separate CPU and EPC memories it may allow more pages to be stored in EPC memory.
Accordingly, there is an unmet need for systems and/or methods that facilitate determining how many memory blocks are used to compress a given image and adjusting memory block size on the fly to mitigate memory waste and reduce processor load, and the like, while overcoming the aforementioned deficiencies.